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XMEGA A [MANUAL]
8077I–AVR–11/2012
12.8
Register Description
12.8.1 STATUS – Status register
Bit 7 – NMIEX: Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the interrupt
handler.
Bit 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 2 – HILVLEX: High-level Interrupt Executing
This flag is set when a high-level interrupt is executing or when the interrupt handler has been interrupted by an NMI. The
flag will be cleared when returning (RETI) from the interrupt handler.
Bit 1 – MEDLVLEX: Medium-level Interrupt Executing
This flag is set when a medium-level interrupt is executing or when the interrupt handler has been interrupted by an
interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
Bit 0 – LOLVLEX: Low-level Interrupt Executing
This flag is set when a low-level interrupt is executing or when the interrupt handler has been interrupted by an interrupt
from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
12.8.2 INTPRI – Interrupt priority register
Bit 7:0 – INTPRI: Interrupt Priority
When round-robin scheduling is enabled, this register stores the interrupt vector of the last acknowledged low-level
interrupt. The stored interrupt vector will have the lowest priority the next time one or more low-level interrupts are
pending. The register is accessible from software to change the priority queue. This register is not reinitialized to its initial
value if round-robing scheduling is disabled, and so if default static priority is needed, the register must be written to zero.
Bit
7
65
43
2
1
0
+0x00
NMIEX
–
HILVLEX
MEDLVLEX
LOLVLEX
Read/Write
R
Initial Value
00
0
Bit
7
6
543210
+0x01
INTPRI[7:0]
Read/Write
R/W
Initial Value
00
000000
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